Signal read circuit

ABSTRACT

In a signal read circuit including a plurality of circuit rows each having a charge amplifier connected to a photoelectric conversion element PD and a CDS circuit  2 S for performing correlated double sampling for an output from the charge amplifier, a dummy circuit row DMY having the same configuration as a circuit row SLT is connected in parallel with this circuit row SLT. By calculating the difference between these circuit rows connected in parallel, offset variations generated in the two circuit rows SLT and DMY can be removed.

TECHNICAL FIELD

[0001] The present invention relates to a signal read circuit forreading out an output from a photoelectric conversion element which is asolid-state image sensor such as an image pickup device or a MOS imagesensor and, more particularly, to a signal read circuit for reading outan output from a photodiode array which monitors light transmittedthrough an optical fiber by wavelength division multiplexing bydemultiplexing the light into a plurality of components.

BACKGROUND ART

[0002] The present inventors have proposed a signal read circuit forreading out an output signal from a photodiode array. This signal readcircuit is described in Japanese Patent Laid-Open No. 10-336526.Recently, WDM (Wavelength Division Multiplexing) optical communicationhas attracted attention, and the development of an apparatus whichdemultiplexes an output from an optical fiber into different wavelengthsand monitors each wavelength component is expected.

DISCLOSURE OF INVENTION

[0003] When the individual wavelength components are input to thephotodiode array, the output from the optical fiber can be monitored ateach wavelength. Although the signal read circuit achieves its superiorcharacteristics in an application like this, the characteristics areunsatisfactory and required to be further improved. Especially when inactual use the temperature of the ambient environment of the sensorchanges, the output offset level fluctuates along with this temperaturechange. This deteriorates the absolute output accuracy. The presentinvention relates to improvements of this prior art, and has as itsobject to provide a signal read circuit capable of lowering the noiselevel of an output signal from a photoelectric conversion element.

[0004] To achieve the above object, a signal read circuit according tothe present invention is a signal read circuit comprising a firstcircuit row having a charge amplifier connected to a photoelectricconversion element and a CDS circuit for performing correlated doublesampling for an output from the charge amplifier, characterized bycomprising a second circuit row having the same arrangement as the firstcircuit row and connected in parallel with the first circuit row,wherein two input terminals of the charge amplifier in the secondcircuit row are open, and output terminals of the first and secondcircuit rows are connected to a subsequent circuit such that an offsetlevel generated in the first circuit row decreases.

[0005] In this signal read circuit, the subsequent circuit calculatesthe difference between the circuit rows, thereby removing offset levelvariations particularly generated in the two circuits when a temperaturechanges. This improves the offset level uniformity of an output signalfrom the photoelectric conversion element. Especially when thisphotoelectric conversion element is made of a compound semiconductor, adark current of the photoelectric conversion element significantlydiffers from one element to another. When a plurality of photoelectricconversion elements are used, therefore, the offset level significantlydiffers from one circuit row to another. In a case like this, thedifference configuration described above effectively functions to reducevariations in this offset level.

[0006] For example, when the signal read circuit further comprises adifferential output circuit for outputting a difference between outputsfrom the first and second circuit rows, offset variations generated inthese two circuit rows can be removed.

[0007] This differential output circuit can comprise a differentialamplifier circuit which has an operational amplifier having an invertinginput terminal, non-inverting input terminal, and output terminal, firstand second resistors interposed between the outputs of the first andsecond circuit rows and the inverting and non-inverting input terminals,respectively, and a third resistor interposed between the outputterminal and the inverting input terminal.

[0008] Also, the differential output circuit preferably comprisesselecting means for selectively connecting the outputs from the first orsecond circuit row to one terminal of a capacitor, and a switch which,when the selecting means selects one of the first and second circuitrows to one terminal of the capacitor, connects the other terminal ofthe capacitor to a fixed potential, and, when the selecting meansconnects the other one of the first and second circuit rows to oneterminal of the capacitor, disconnects the other terminal of thecapacitor from the fixed potential. In this arrangement, fluctuations inthe output signal level caused by temperature changes can be suppressed,since the temperature dependence of a capacitor is much lower than thatof a resistor.

[0009] Instead of the differential output circuit, the signal readcircuit can further comprise calculating means for calculating thedifference between the outputs from the first and second circuit rows.This calculating means can be a computer.

[0010] The first and second circuit rows are preferably formed on thesame semiconductor substrate. This arrangement can achieve circuitcharacteristics more uniform than when these circuits are formed ondifferent substrates. When the differences between the outputs fromthese circuits are calculated, therefore, the offset variations can befurther reduced.

[0011] In the signal read circuit, a third circuit row having an openinput terminal to which no input signal is applied, and having the sameconfiguration as that of the first circuit row, is preferably connectedin parallel with the first circuit row on the semiconductor substrate.In this case, an output from this third circuit row having similaroutput characteristics can be used.

[0012] In particular, the first circuit row is desirably placed betweenthe second and third circuit rows. In this case, the output from thefirst circuit row on the semiconductor substrate can be regarded assubstantially equal to the average value of the outputs from the secondand third circuit rows. Accordingly, the influence of the formationpositions of these circuit rows can be suppressed. That is, the signalread circuit according to the present invention preferably comprises adifferential output circuit for outputting a difference between anaverage value of the outputs from the second and third circuit rows andthe output from the first circuit row. This differential output circuitneed not be formed on the same semiconductor substrate. Additionally,the difference can also be calculated by inputting these outputs to acalculating means such as a computer.

BRIEF DESCRIPTION OF DRAWINGS

[0013]FIG. 1 is block diagram showing the configuration of a systemincluding a semiconductor device and a signal read circuit;

[0014]FIG. 2 is a circuit diagram showing one of photodiodes PD used inthe semiconductor device;

[0015]FIG. 3 is a circuit diagram showing one of the photodiodes PD usedin the semiconductor device;

[0016]FIG. 4 is a circuit diagram of a charge amplifier 2C;

[0017]FIG. 5 is a circuit diagram of a CDS circuit 2S;

[0018]FIG. 6 is a circuit diagram of a final-stage amplifier 2A;

[0019]FIG. 7 is a circuit diagram showing an example of a differentialoutput circuit 2D;

[0020]FIG. 8 is a circuit diagram showing another example of thedifferential output circuit 2D;

[0021]FIG. 9 is a timing chart in the signal read circuit when thedifferential output circuit 2D shown in FIG. 7 is used;

[0022]FIG. 10 is a timing chart in the signal read circuit when thedifferential output circuit 2D shown in FIG. 8 is used;

[0023]FIG. 11 is a block diagram showing another system configurationfor calculating a difference;

[0024]FIG. 12 is a block diagram showing the system configuration of asignal read circuit according to another embodiment; and

[0025]FIG. 13 is a block diagram showing the configuration of a systemincluding a semiconductor device and a signal read circuit according tostill another embodiment.

BEST MODE OF CARRYING OUT THE INVENTION

[0026] A signal read circuit according to an embodiment will beexplained below together with a semiconductor device which supplies aninput signal to the signal read circuit and comprises a plurality ofphotoelectric conversion elements. The same reference numerals denotethe same parts, and a duplicate explanation thereof will be omitted.

[0027]FIG. 1 is a block diagram showing the configuration of a systemincluding the semiconductor device and the signal read circuit.

[0028] This semiconductor device is fabricated by forming a plurality ofphotodiodes PD on a semiconductor substrate 1 made of a compoundsemiconductor (InGaAs). In the end portion of this semiconductorsubstrate, signal output electrode pads OUT connected to the individualphotodiodes PD are formed.

[0029] The signal read circuit has a plurality of circuit rows in eachof which a charge amplifier 2C, a correlated double sampling circuit (tobe referred to as a CDS circuit hereinafter) 2S, and a switch FET(S)which is a MOSFET (Field-Effect Transistor) are connected in series. Thenumber of circuit rows is larger than the number of photodiodes PD; inthis embodiment, the number of photodiodes PD is 5, and the number ofcircuit rows is 6. That is, five of the six circuit rows correspond tothe photodiodes PD, and one of them is a dummy circuit row. A shiftregister 2SF sequentially switches the switches FET(S), therebysequentially connecting these circuit rows arranged in a main circuitportion MAIN to an amplifier 2A.

[0030] The signal read circuit is formed on a semiconductor substrate 2.In the end portion of this semiconductor substrate 2, signal inputelectrode pads IN which function as the input terminals of the fivecircuit rows are formed. No electrode pad is formed for the oneremaining circuit row. The semiconductor substrate 2 is made of Si, andthe signal read circuit is fabricated on this substrate 2.

[0031] Note that each of the semiconductor substrates 1 and 2 can bemade of a compound semiconductor or Si. Note also that eachsemiconductor substrate contains not only a semiconductor material butalso an insulator for forming protective films and capacitors and ametal for forming interconnects.

[0032] The photodiode PD and the charge amplifier 2C are connected viathe signal output electrode pad OUT, a bonding wire W, and the signalinput electrode pad IN. Since the influence of the parasitic capacitanceof the charge amplifier 2C can be suppressed more as the length of thebonding wire W decreases, the semiconductor device and the signal readcircuit are preferably formed on the same semiconductor substrate. Inthis embodiment, however, the semiconductor device and the signal readcircuit are formed on the different semiconductor substrates 1 and 2,respectively.

[0033] Accordingly, an output from each photodiode PD is input to thecharge amplifier 2C, the CDS circuit 2S, and the switch FET(S) throughthe wire W, and then to a differential output circuit 2D via theamplifier 2A. Assume that the circuit row (2C, 2S, FET(S), and 2A) inwhich the switch FET(S) is ON is a selected circuit row SLT. The inputterminal of a dummy circuit row DMY having the same configuration asthis selected circuit row SLT is open, so no input signal is given tothis input terminal. Noise components generated in these two circuitrows SLT and DMY are input to the differential output circuit 2D.

[0034] That is, in this signal read circuit including the first circuitrow SLT having the charge amplifier 2C connected to the photoelectricconversion element PD and the CDS circuit 2S which performs correlateddouble sampling for an output from the charge amplifier 2C, the inputterminal is open, so no input signal is given to this input terminal. Inaddition, the second circuit row DMY having the same configuration asthe first circuit row SLT is formed in parallel with this first circuitrow SLT. This means that the two input terminals of the charge amplifierin the second circuit row DMY are open. The output terminals of thefirst and second circuit rows SLT and DMY are connected to thesubsequent circuit, so as to decrease the offset level generated in thefirst circuit row SLT. In this embodiment, this subsequent circuit isthe differential output circuit.

[0035] In practice, the final output offset voltage in 2A of FIG. 1varies if the temperature fluctuates in the ambient environment of thesensor owing to, e.g., a dark current generated by a parasitic diodepresent on the semiconductor substrate 2 in the input portion of eachcharge amplifier 2C, or the offset voltage temperature dependence of theamplifier 2A itself.

[0036] Since, however, offset variations of the first and second circuitrows are substantially equal, these offset variations can be reduced bycalculating the difference between the outputs from these circuit rows.An offset level variation is particularly conspicuous when thephotoelectric conversion element PD is made of a compound semiconductor.This circuit can effectively reduce this variation.

[0037] This difference can also be calculated by a computer or the like.However, this embodiment includes the differential output circuit 2D foroutputting the difference between the outputs from the first circuit rowSLT and the second circuit row DMY, thereby removing any offsetvariations generated in these two circuit rows. Accordingly, the offsetlevel uniformity of output signals from the photoelectric conversionelements can be improved.

[0038] Since the first and second circuit rows SLT and DMY are formed onthe same semiconductor substrate 2, it is possible to obtain circuitcharacteristics more uniform than when these circuit rows are formed ondifferent semiconductor substrates. Therefore, when the differencebetween the outputs from these circuit rows is calculated,temperature-dependent offset variations can be well reduced.

[0039] The shift register 2SF is driven by an output pulse from a timinggenerator 4. This timing generator 4 generates pulse signals necessaryto drive this apparatus, including the driving signal of the shiftregister 2SF, from a reference-frequency clock signal output from anoscillator 3 such as a quartz oscillator or a multivibrator.

[0040] Various arrangements are possible as the arrangement of eachcircuit element. Preferred examples of these arrangements will beexplained below. Although only one of the plurality of circuit elementswill be explained, the other circuit elements have the same arrangement,so a detailed description thereof will be omitted.

[0041] First, the photoelectric conversion element PD will be describedbelow.

[0042] Each of FIGS. 2 and 3 is a circuit diagram showing one of thephotodiodes PD used in the semiconductor device described above.Referring to FIG. 2, the anode of the photodiode PD is grounded, whileits cathode is connected to the output terminal OUT. Referring to FIG.3, the cathode of the photodiode PD is grounded, while its anode isconnected to the output terminal OUT.

[0043] In FIGS. 2 and 3, the potential of one of the anode and cathodeis a fixed potential (ground potential) Vref. However, this potentialVref can also be another fixed potential, e.g., ½ the power supplypotential (VDD) of the signal read circuit.

[0044] To use the photodiode PD shown in each of FIGS. 2 and 3, areverse bias or zero bias is applied to the photodiode PD. That is, thecathode potential is set to be higher than or equal to the anodepotential.

[0045] The photoelectric conversion element can also be an element, suchas a CCD, in which electric charge is stored in accordance withincidence of light into a potential well formed in the surface of asemiconductor substrate. Furthermore, a photomultiplier tube can be usedas the photoelectric conversion element.

[0046] The charge amplifier 2C will be described next.

[0047]FIG. 4 is a circuit diagram of the charge amplifier 2C. Thischarge amplifier 2C includes an operational amplifier OP(2C). Thenon-inverting input terminal of this operational amplifier OP(2C) isconnected to the fixed potential Vref. The inverting input terminal ofthe operational amplifier OP(2C), to which an output from the photodiodePD is input via the electrode pad IN, is connected to an output terminalOUT(2C) via a capacitor C(2C).

[0048] That is, the output of the operational amplifier OP(2C) is fedback to the input via the capacitor C(2C). A switch FET(R) for reset isconnected in parallel with the capacitor C(2C). When this switch FET(R)is connected (ON), the capacitor C(2C) is short-circuited (reset); whenthe switch FET(R) is disconnected (OFF), electric charge is stored inthe capacitor C(2C) (the capacitor C(2C) is set in a storage state).

[0049] The power supply voltage VDD and the fixed potential Vref of thecharge amplifier C are so set that a reverse bias or zero bias isapplied to the photodiode PD.

[0050] The CDS circuit 2S will be explained below.

[0051]FIG. 5 is a circuit diagram of this CDS circuit 2S. The CDScircuit 2S of this embodiment includes a sample and hold circuit HLD.The CDS circuit 2S has an input (inverting input terminal) connected tothe output OUT of the charge amplifier 2C in the preceding stage, and acapacitor C1(2S) connected between this input terminal and anoperational amplifier OP(2S). The output of the operational amplifierOP(2S) is fed back to the input via a capacitor C2(2S). Thenon-inverting input terminal of the operational amplifier OP(2S) isconnected to the fixed potential Vref. A switch FET(C) for clamping isconnected in parallel with the capacitor C2(2S). When this switch FET(C)is connected (ON), the capacitor C2(2S) is short-circuited (clamped);when the switch FET(C) is disconnected (OFF), electric charge is storedin the capacitor C2(2S) (the capacitor C(2S) is set in a storage state).

[0052] When the charge amplifier 2C is reset and the CDS circuit 2S isclamped, an offset level of the charge amplifier 2C appears at theoutput OUT(2C) of the charge amplifier 2C. If immediately after that thecharge amplifier 2C is set in the storage state while the CDS circuit 2Sis kept clamped and then the CDS circuit 2S is set in the storage state,electric charge proportional to a potential change in the outputterminal OUT(2C) since the CDS circuit 2S is set in the storage state isstored in the capacitor C2(2S), thereby eventually removing the offsetlevel from this output. That is, correlated double sampling isperformed.

[0053] An output OUT′(2S) of the operational amplifier OP(2S) is held bythe sample and hold circuit HLD. More specifically, the electric chargestored in the capacitor C2(2S) is stored in a holding capacitor C(H) byconnecting (turning on) a switch FET(H) on the input side of the sampleand hold circuit HLD. After that or at the same time, a switch FET′(G)present between one terminal of the output side of the holding capacitorC(H) and the fixed potential Vref is connected, thereby setting thisterminal of the output side of the holding capacitor C(H) at the fixedpotential Vref. Subsequently, the two switches FET(H) and FET′(G) aredisconnected to hold the electric charge such that one terminal of theinput side of the holding capacitor C(H) is at a potential φC. Afterthat, the main body portion of the CDS circuit 2S is clamped. However,this portion is disconnected from the sample and hold circuit HLD andhence has no influence on the held electric charge.

[0054] The final-stage amplifier 2A will be described below.

[0055]FIG. 6 is a circuit diagram of the final-stage amplifier 2A. Theoutput OUT(2S) of the CDS circuit 2S having the sample and hold circuitHLD is the input (inverting input terminal) of the final-stage amplifier2A. These output and input are connected by connecting (turning on) aswitch FET(S) for circuit row selection present between them. Theconfiguration of the final-stage amplifier 2A is the same as the chargeamplifier 2C; instead of the operational amplifier OP(2C), the capacitorC(2C), and the reset switch FET(R) in the charge amplifier 2C, thefinal-stage amplifier 2A includes an operational amplifier OP(2A), acapacitor C(2A), and a reset switch FET(FR). By turning on and off thereset switch FET(FR), the final-stage amplifier 2A functions similar tothe charge amplifier 2C, and outputs to the output OUT a potentialproportional to the output from the CDS circuit 2S.

[0056] The differential output circuit 2D will be described below.

[0057]FIG. 7 is a circuit diagram showing an example of the differentialoutput circuit 2D. This differential output circuit 2D has anoperational amplifier OP(2D) having an inverting input terminal,non-inverting input terminal, and output terminal. The outputs from thefirst and second circuit rows described above, i.e., the output from thefinal-stage amplifier 2A connected to the circuit row SLT selected bythe selecting means FET(S) and the output from the final-stage amplifier2A in the dummy circuit row DMY are input to the input terminals of theoperational amplifier OP(2D) via resistors R1 and R2. The output of thisoperational amplifier OP(2D) is fed back to the input via a feedbackresistor Rf. The non-inverting input terminal of the operationalamplifier OP(2D) is connected to the fixed potential Vref.

[0058] That is, this differential output circuit 2D is a differentialamplifier having the first and second resistors R1 and R2 interposedbetween the input terminal of the operational amplifier OP(2D) and theoutputs of the circuit rows SLT and DMY, respectively, and the thirdresistor Rref interposed between the output terminal and the invertinginput terminal of the operational amplifier OP(2D). The differentialoutput circuit 2D outputs the difference between the input voltages fromthe output terminal OUT(2D).

[0059]FIG. 8 is a circuit diagram showing another example of thedifferential output circuit 2D. This differential output circuit 2Dincludes selecting means FET(D1) and FET(D2) for selectively connectingthe output from the first circuit row SLT or the second circuit row DMYto one terminal of a capacitor C(2D). These selecting means FET(D1) andFET(D2) are switches such as FETs. By turning on and off the switchesFET, the circuit rows SLT or DMY is connected to the capacitor C(2D).

[0060] When one of the first circuit row SLT and the second circuit rowDMY is connected to one terminal of the capacitor C(2D) in a period T1,a switch FET(G) of this differential output circuit 2D connects theother terminal of the capacitor C(2D) to the fixed potential Vref.

[0061] When the other one of the first circuit row SLT and the secondcircuit row DMY is connected to one terminal of the capacitor C(2D) in aperiod T2 after the period T1, the switch FET(G) of the differentialoutput circuit 2D disconnects the other terminal of the capacitor C(2D)from the fixed potential Vref. The timings of connection anddisconnection are the same, or the disconnection timing is slightlyearlier. Accordingly, the potential at the other terminal of thecapacitor C(2D) becomes proportional to the potential difference betweenthe output signals from the first and second circuit rows SLT and DMY.This potential is output to the outside via a buffer amplifier B(2D)connected to the subsequent stage.

[0062] In this differential output circuit 2D, the temperaturedependence of the capacitor is much lower than that of the resistor.Therefore, fluctuations of the output signal level caused by temperaturechanges can be suppressed more than in the aforementioned differentialoutput circuit.

[0063]FIGS. 9 and 10 are timing charts of the potentials in the signalread circuit when the differential output circuits 2D shown in FIGS. 7and 8 are used. These timings are generated by the timing generator 4(FIG. 1). Note that the timings relating to the selected circuit row SLTare described with SLT attached, and those relating to the dummy circuitDMY are described with DMY attached. Electric charges from the pluralityof photodiodes PD are stored in the individual circuit rows at the sametime by the charge amplifiers 2C and the CDS circuits 2S during anintegral period shown in FIGS. 9 and 10. The stored electric charges areheld by connecting and disconnecting the switches FET(H) and FET′(G),and sequentially read out from the circuit rows.

[0064] In the above configuration, the potential difference between theselected circuit row SLT and the dummy circuit row DMY is output byusing the differential output circuit 2D. However, the followingconfiguration can also be used.

[0065]FIG. 11 is a block diagram showing another system configurationfor obtaining the difference. The outputs OUT(2A) of the final-stageamplifiers 2A in the selected circuit row SLT and the dummy circuit rowDMY are input to A/D converters 10 connected in parallel. After beingconverted from analog signals into digital signals, these outputs areinput to a computer 11. This computer 11 calculates the differencebetween the outputs, indicated by the two input digital signals, fromthe circuit rows SLT and DMY. That is, instead of the differentialoutput circuit 2D, this signal read circuit includes a calculating means11 for calculating the difference between the outputs from the first andsecond circuit rows SLT and DMY.

[0066]FIG. 12 is a block diagram showing the system configuration of asignal read circuit according to another embodiment. The signal readcircuit of this embodiment is the same as that shown in FIG. 1 exceptthat the circuit includes another dummy circuit row DMY′, and theaverage value of two dummy circuits DMY and DMY′ is input to adifferential output circuit 2D.

[0067] That is, the input terminal of this signal read circuit is open,so no input signal is applied. In addition, the third circuit row (dummycircuit row) DMY′ having the same arrangement as a first circuit row SLTis connected in parallel with the first circuit row on the samesemiconductor substrate 2. In this embodiment, an output from this thirdcircuit row DMY′ having similar output characteristics can be used.

[0068] The first circuit row SLT is placed between the second circuitrow DMY and the third circuit row DMY′. Therefore, an output from thefirst circuit row SLT on the semiconductor substrate 2 can be regardedas substantially equal to the average value of the outputs from thesecond and third circuit rows DMY and DMY′. This suppresses theinfluence of the positions of these circuit rows.

[0069] That is, this signal read circuit includes an average valueoutput circuit 2AV for calculating the average value of the outputs fromthe second and third circuit rows DMY and DMY′, and the differentialoutput circuit 2D for outputting the difference between this averagevalue and the output from the first circuit row SLT. Note that thedifferential output circuit 2D need not be formed on the samesemiconductor substrate. Note also that the difference can also becalculated by inputting these outputs to a calculating means such as acomputer.

[0070] The semiconductor device according to each of the aboveembodiments is a line sensor in which the plurality of photodiodes PDare one-dimensionally arranged. However, these photodiodes PD can alsobe two-dimensionally arranged.

[0071]FIG. 13 is a block diagram showing the configuration of a systemincluding a semiconductor device and a signal read circuit according tostill another embodiment. In this circuit, the arrangement of the signalread circuit is the same as that shown in FIG. 1, and only thearrangement of the semiconductor device for photoelectric conversion isdifferent from that shown in FIG. 1. The arrangement of each verticalphotodiode string is the same as that shown in FIG. 1 except that aswitch FET is interposed between each photodiode PD and an outputterminal OUT.

[0072] By connecting this switch FET, the photodiode PD of each verticalstring is connected to the corresponding output terminal OUT to functionsimilar to that shown in FIG. 1. A plurality of such photodiode stringsare horizontally arranged adjacent to each other. These verticalphotodiode strings horizontally adjacent to each other are sequentiallyselected by signals from a shift register 1SF. The photodiodes PD of theselected photodiode string are connected to the output terminals OUT.With this configuration, an optical input having a two-dimensionalspread can be converted into an electrical signal and output from theoutput terminals OUT. Note that in this system, the arrangement of thesignal read circuit 2 can be modified as in the above embodiments.

[0073] The above signal read circuit can be applied to a signal readcircuit for reading out an output from a photoelectric conversionelement which is a solid-state image sensor such as an image pickupdevice or a MOS image sensor. More specifically, the above signal readcircuit is applicable to a signal read circuit for reading out an outputfrom a photodiode array which monitors light transmitted through anoptical fiber by wavelength division multiplexing by demultiplexing thelight into a plurality of components.

[0074] As described above, the signal read circuit of the presentinvention can reduce offset variations of an output signal from aphotoelectric conversion element.

Industrial Applicability

[0075] The present invention can be used in a signal read circuit forreading out a signal from a photoelectric conversion element.

1. A signal read circuit comprising: a first circuit row having a chargeamplifier connected to a photoelectric conversion element and a CDScircuit for performing correlated double sampling for an output fromsaid charge amplifier; and a second circuit row having the samearrangement as said first circuit row and connected in parallel withsaid first circuit row, wherein two input terminals of said chargeamplifier in said second circuit row are open, and output terminals ofsaid first and second circuit rows are connected to a subsequent circuitsuch that an offset level generated in said first circuit row decreases.2. A signal read circuit according to claim 1, characterized in thatsaid subsequent circuit comprises a differential output circuit foroutputting a difference between outputs from said first and secondcircuit rows.
 3. A signal read circuit according to claim 2,characterized in that said differential output circuit comprises adifferential amplifier circuit which has an operational amplifier havingan inverting input terminal, non-inverting input terminal, and outputterminal, first and second resistors interposed between the outputs ofsaid first and second circuit rows and said inverting and non-invertinginput terminals, respectively, and a third resistor interposed betweensaid output terminal and said inverting input terminal.
 4. A signal readcircuit according to claim 2, characterized in that said differentialoutput circuit comprises: selecting means for selectively connecting theoutput from said first or second circuit row to one terminal of acapacitor, and a switch which, when said selecting means selects one ofsaid first and second circuit rows to one terminal of said capacitor,connects the other terminal of said capacitor to a fixed potential, and,when said selecting means connects the other one of said first andsecond circuit rows to one terminal of said capacitor, disconnects theother terminal of said capacitor from the fixed potential.
 5. A signalread circuit according to claim 1, characterized by further comprisingcalculating means for calculating the difference between the outputsfrom said first and second circuit rows.
 6. A signal read circuitaccording to claim 1, characterized in that said first and secondcircuit rows are formed on the same semiconductor substrate.
 7. A signalread circuit according to claim 6, characterized in that a third circuitrow having an open input terminal and having the same configuration asthat of said first circuit row is connected in parallel with said firstcircuit row on said semiconductor substrate.
 8. A signal read circuitaccording to claim 7, characterized in that said first circuit row isplaced between said second and third circuit rows.
 9. A signal readcircuit according to claim 8, characterized by further comprising adifferential output circuit for outputting a difference between anaverage value of the outputs from said second and third circuit rows andthe output from said first circuit row.